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LTC1143/LTC1143L LTC1143L-ADJ Dual High Efficiency SO-16 Step-Down Switching Regulator Controllers DESCRIPTION
The LTC1143 series is a dual step-down switching regulator controller featuring automatic Burst ModeTM operation to maintain high efficiencies at low output currents. This device is composed of two separate regulator blocks, each driving an external power MOSFET at switching frequencies up to 400kHz using a constant off-time current mode architecture. Both fixed and adjustable voltages are available. The operating current level for both regulators is userprogrammable via an external current sense resistor. Wide input supply range allows operation from 4V to 14V (16V maximum). The LTC1143L and LTC1143L-ADJ extend operation to VIN = 3.5V. 100% duty cycle provides low dropout regulation limited only by the RDS(ON) of the external MOSFET and resistance of the inductor and current sense resistor. The LTC1143 series is ideal for applications requiring dual output voltages with high conversion efficiencies over a wide load current range in a small amount of board space.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation.
FEATURES
s
s s
s
s s s
s s
Dual Outputs LTC1143, LTC1143L: 3.3V, 5V LTC1143L-ADJ: Dual Adjustable Very High Efficiency: Over 95% Possible Current Mode Operation for Excellent Line and Load Transient Response High Efficiency Maintained over Three Decades of Output Current Low Standby Current at Light Loads: 160A/Output Logic-Controlled Shutdown (LTC1143, LTC1143L) Wide VIN Range: 3.5V to 16V (LTC1143L, LTC1143L-ADJ) Very Low Dropout Operation: 100% Duty Cycle Available in Narrow 16-Pin SO Package
APPLICATIONS
s s s s s
Personal Digital Assistants Notebook and Palmtop Computers Battery-Operated Digital Devices Portable Instruments DC Power Distribution Systems
TYPICAL APPLICATION
+
CIN1 22F 25V x2 0.22F P1A 4 1 1000pF COUT1 220F 10V x2 13 VIN1 P-DRIVE 1 SENSE + 1
VIN 4V TO 14V
5 VIN2 P-DRIVE 2 SENSE + 2 LTC1143L-ADJ SENSE - 2 P1B 12 9 1000pF 8 D2 MBRS320T3 R4 49.9k 1% L2 27H
VOUT1 3.3V/2A
RSENSE1 0.05
L1 27H
+
R2 82.5k 1%
16 D1 MBRS320T3 2 100pF
SENSE - 1
VFB1 GND1 3 CT1 14 ITH1 15 RC1 1k CC1 CC2 3300pF 3300pF ITH2 7 RC2 1k CT2 300pF CT2 6
VFB2 GND2 11
R1 49.9k 1%
L1, L2: SUMIDA CDRH125-270 P1: SILICONIX Si4953DY/FAIRCHILD NDS8947 RSENSE1, RSENSE2: DALE WSL-2010-.05
CT1 300pF
Figure 1. High Efficiency Dual 3.3V/2.5V Regulator
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10
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+
0.22F
CIN2 22F 25V x2 RSENSE2 0.05
VOUT2 2.5V/2A
+
R3 49.9k 1%
COUT2 220F 10V x2
100pF
1143 F01
1
LTC1143/LTC1143L LTC1143L-ADJ
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (Pins 5,13) ............... 16V to -0.3V Continuous Output Current (Pins 4,12) ................ 50mA Sense Voltages (Pins 1, 8, 9, 16) VIN 12.7V .......................................... 13V to - 0.3V VIN < 12.7V .............................. (VIN + 0.3V) to - 0.3V Shutdown Voltage (LTC1143, LTC1143L, Pins 2, 10)...........7V to - 0.3V VFB Current (LTC1143L-ADJ, Pins 2, 10) ............... 1mA Operating Temperature Range Ambient .................................................. 0C to 70C Extended Commercial (Note 4) ........... -40C to 85C Junction Temperature (Note 1) ............................. 125C Storage Temperature Range .................. -65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
PACKAGE/ORDER INFORMATION
TOP VIEW SENSE+3 1 16 SENSE- 3
ORDER PART NUMBER LTC1143CS LTC1143LCS
SHUTDOWN 3 2 GND3 3 P-DRIVE 3 4 VIN5 5 CT5 6 ITH5 7 SENSE-5 8
15 ITH3 14 CT3 13 VIN3 12 P-DRIVE 5 11 GND5 10 SHUTDOWN 5 9 SENSE+5
S PACKAGE 16-LEAD PLASTIC SO
TJMAX = 125C, JA = 95C/W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER V2, V10 I2, I10 VOUT Feedback Voltage (LTC1143L-ADJ) Feedback Current (LTC1143L-ADJ) Regulated Output Voltage (LTC1143/LTC1143L) 3.3V Output 5V Output Output Voltage Line Regulation Output Voltage Load Regulation LTC1143/LTC1143L 3.3V Output 5V Output Output Ripple (Burst Mode) I5, I13 Input DC Supply Current (Note 2) LTC1143: Normal Mode Sleep Mode Shutdown LTC1143L: Normal Mode Sleep Mode Shutdown LTC1143L-ADJ: Normal Mode Sleep Mode VIN = 9V
CONDITIONS
q q
VIN3, VIN5 = 9V, V2 = V10 = 0V ILOAD = 700mA ILOAD = 700mA VIN = 7V to 12V, ILOAD = 50mA V2 = V10 = 0V 5mA < ILOAD < 2.0A 5mA < ILOAD < 2.0A ILOAD = 0A V2 = V10 = 0V, 4V < VIN < 12V V2 = V10 = 0V, 4V < VIN3 < 12V, 6V < VIN5 < 12V V2 = V10 = 2.1V, 4V < VIN < 12V V2 = V10 = 0V, 3.5V < VIN < 12V V2 = V10 = 0V, 3.5V < VIN3 < 12V, 6V < VIN5 < 12V V2 = V10 = 2.1V, 3.5V < VIN < 12V 3.5V < VIN < 12V 3.5V < VIN < 12V, VOUT 3.3V
VOUT
2
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WW
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TOP VIEW SENSE +1 1 VFB1 2 GND1 3 P-DRIVE 1 4 VIN2 5 CT2 6 ITH2 7 SENSE -2 8 16 SENSE-1 15 ITH1 14 CT1 13 VIN1 12 P-DRIVE 2 11 GND2 10 VFB2 9 SENSE +2
ORDER PART NUMBER LTC1143LCS-ADJ
S PACKAGE 16-LEAD PLASTIC SO
TJMAX = 125C, JA = 95C/W
TA = 25C, VIN = 10V unless otherwise noted.
MIN 1.21 TYP 1.25 0.2 3.23 4.90 -40 3.33 5.05 0 MAX 1.29 1 3.43 5.20 40 UNITS V A V V mV
q q
q q
40 60 50 1.6 160 10 1.6 160 10 1.6 160
65 100
mV mV mVP-P
2.1 230 20 2.1 230 20 2.1 230
mA A A mA A A mA A
LTC1143/LTC1143L LTC1143L-ADJ ELECTRICAL CHARACTERISTICS
SYMBOL V1 to V16, V8 to V9 PARAMETER Current Sense Threshold Voltage LTC1143/LTC1143L CONDITIONS V2 = V10 = 0V VSENSE - = VOUT + 100mV (Forced) VSENSE - = VOUT - 100mV (Forced) VSENSE- = 5V, VFB = VOUT /4 + 25mV (Forced) VSENSE- = 5V, VFB = VOUT /4 - 25mV (Forced)
TA = 25C, VIN = 10V unless otherwise noted.
MIN TYP MAX UNITS
q q
130 130 0.5
LTC1143L-ADJ V2, V10 I2, I10 I6, I14 tOFF tr, tf Shutdown Pin Threshold LTC1143/LTC1143L Shutdown Pin Input Current LTC1143/LTC1143L CT Pin Discharge Current Off-Time (Note 3) Driver Output Transition Times
25 150 25 150 0.8 1.2
170 170 2 5 90 10 6 200
mV mV mV mV V A A A s ns
0V < VSHUTDOWN = < 8V, VIN3, VIN5 = 16V VOUT in Regulation, VSENSE- = VOUT VOUT = 0V CT = 390pF, ILOAD = 700mA CL = 3000pF (Pins 4, 12), VIN = 6V 50 4
70 2 5 100
-40C TA 85C (Note 4), VIN = 10V unless otherwise noted.
V2, V10 VOUT Feedback Voltage (LTC1143L-ADJ) Regulated Output Voltage LTC1143/LTC1143L 3.3V Output 5V Output Input DC Supply Current (Note 2) LTC1143: Normal Mode Sleep Mode Shutdown LTC1143L: Normal Mode Sleep Mode Shutdown LTC1143L-ADJ: Normal Mode Sleep Mode Current Sense Threshold Voltage LTC1143/LTC1143L VIN = 9V VIN3, VIN5 = 9V ILOAD = 700mA ILOAD = 700mA V2 = V10 = 0V, 4V < VIN < 12V V2 = V10 = 0V, 4V < VIN3 < 12V, 6V < VIN5 < 12V V2 = V10 = 2.1V, 4V < VIN < 12V V2 = V10 = 0V, 3.5V < VIN < 12V V2 = V10 = 0V, 3.5V < VIN3 < 12V, 6V < VIN5 < 12V V2 = V10 = 2.1V, 3.5V < VIN < 12V 3.5V < VIN < 12V 3.5V < VIN < 12V, VOUT 3.3V V2 = V10 = 0V VSENSE - = VOUT + 100mV (Forced) VSENSE - = VOUT - 100mV (Forced) VSENSE- = 5V, VFB = VOUT /4 + 25mV (Forced) VSENSE- = 5V, VFB = VOUT /4 - 25mV (Forced) 3.17 4.85 3.33 5.05 1.6 160 10 1.6 160 10 1.6 160 3.43 5.20 2.4 260 22 2.4 260 22 2.4 260 V V mA A A mA A A mA A 1.20 1.25 1.30 V
I5, I13
V1 to V16, V8 to V9
125 125 0.55
LTC1143L-ADJ V2, V10 Shutdown Pin Threshold LTC1143/LTC1143L
25 150 25 150 0.8
185 185 2
mV mV mV mV V
The q denotes specifications which apply over the specified temperature range. Note 1: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC1143 series: TJ = TA + (PD * 125C/W) Note 2: This supply current is for one regulator block. Total supply current is the sum of Pin 5 and Pin 13 currents. Dynamic supply current
is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 3: In applications where RSENSE is placed at ground potential, the off-time increases approximately 40%. Note 4: The LTC1143 series is guaranteed to meet specified performance from 0C to 70C and is designed, characterized and expected to meet these extended temperature limits, but is not tested at -40C to 85C.
3
LTC1143/LTC1143L LTC1143L-ADJ TYPICAL PERFORMANCE CHARACTERISTICS
5V Output Efficiency
100 VIN = 6V 95
EFFICIENCY (%)
95 VIN = 5V EFFICIENCY (%) 90 85 80 75 70 1 10 100 1000
LTC1143 G02
VIN = 10V 85 80 75 70 1 10 100 1000
LTC1143 G01
EFFICIENCY (%)
90
LOAD CURRENT (mA)
3.3V Efficiency vs Input Voltage
100 98 96 VOUT = 3.3V
40 30 20
EFFICIENCY (%)
94
VOUT (mV)
92 90 88 86 84 82 80 0 4 12 8 INPUT VOLTAGE (V) 16
LTC1143 G04
ILOAD = 1A ILOAD = 100mA
0 -10 -20 -30 -40 0 4 12 8 INPUT VOLTAGE (V) 16
LTC1143 G05
VOUT (mV)
DC Supply Current
2.1 1.8
SUPPLY CURRENT (mA)
NOT INCLUDING GATE CHARGE CURRENT ACTIVE MODE
PINS 5, 13
NORMALIZED FREQUENCY
1.5 1.2 0.9 0.6 0.3 0 0 2 4
SUPPLY CURRENT (A)
PER REGULATOR BLOCK
SLEEP MODE 8 10 12 14 6 INPUT VOLTAGE (V) 16 18
4
UW
LTC1143 * G07
3.3V Output Efficiency
100
100 98 96 94 92 90 88 86 84 82 80
5V Efficiency vs Input Voltage
VOUT = 5V
ILOAD = 1A
VIN = 10V
ILOAD = 100mA
0
4
LOAD CURRENT (mA)
12 8 INPUT VOLTAGE (V)
16
1143 G03
Line Regulation
20
VOUT = 5V ILOAD = 1A
Load Regulation
RSENSE = 0.05 0 -20 -40 -60 -80 -100 0 0.5 1.5 2.0 1.0 LOAD CURRENT (A) 2.5
LTC1143 G06
VIN = 6V VIN = 12V
10
VIN = 6V VIN = 12V VOUT = 5V VOUT = 3.3V
Supply Current in Shutdown
20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 INPUT VOLTAGE (V) 16 18
0.2 0 1.6
Operating Frequency vs VIN - VOUT
VOUT = 5V 1.4 0C 1.2 25C 1.0 0.8 0.6 0.4 70C
PER LTC1143/LTC1143L REGULATOR BLOCK PINS 5, 13 VSHUTDOWN = 2V
0
2
4
6
8
10
12
(VIN - VOUT) VOLTAGE (V)
LTC1143 G08
LTC1143 G09
LTC1143/LTC1143L LTC1143L-ADJ TYPICAL PERFORMANCE CHARACTERISTICS
Gate Charge Supply Current
14 12
GATE CHARGE CURRENT (mA)
10 8 6 4
SENSE VOLTAGE (mV)
QP = 100nC
OFF-TIME (s)
QP = 29nC 2 0 20 80 200 260 140 OPERATING FREQUENCY (kHz)
LTC1143 G10
PIN FUNCTIONS
LTC1143/LTC1143L
SENSE+3 (Pin 1): The (+) Input to the 3.3V Section Current Comparator. A built-in offset between Pins 1 and 16 in conjunction with RSENSE 3 sets the current trip threshold for the 3.3V section. SHUTDOWN 3 (Pin 2): When grounded, the 3.3V section operates normally. Pulling Pin 2 high holds the MOSFET off and puts the 3.3V section in micropower shutdown mode. Requires CMOS logic level signal with tr, tf < 1s. Do not "float" Pin 2. GND3 (Pin 3): 3.3V Section Ground. Two independent ground lines must be routed separately from other grounds to: 1) the (-) terminal of the 3.3V section output capacitor and 2) the cathode of the Schottky diode D1 and (-) terminal of CIN3 (see Figure 9). P-DRIVE 3 (Pin 4): High Current Drive for Top P-Channel MOSFET, 3.3V Section. Voltage swing at this pin is from VIN3 to ground. VIN5 (Pin 5): Supply Pin, 5V Section. Must be closely decoupled to 5V power ground Pin 11. CT5 (Pin 6): External capacitor CT5 from Pin 6 to ground sets the operating frequency for the 5V section. (The actual frequency is also dependent upon the input voltage.) ITH5 (Pin 7): Gain Amplifier Decoupling Point, 5V Section. The 5V section current comparator threshold increases with the Pin 7 voltage. SENSE- 5 (Pin 8): Connects to internal resistive divider which sets the output voltage for the 5V section. Pin 8 is also the (-) input for the current comparator on the 5V section. SENSE+ 5 (Pin 9): The (+) Input to the 5V Section Current Comparator. A built-in offset between Pins 9 and 8 in conjunction with RSENSE 5 sets the current trip threshold for the 5V section. SHUTDOWN 5 (Pin 10): When grounded, the 5V section operates normally. Pulling Pin 10 high holds the 5V section MOSFET off and puts the 5V section in micropower shutdown mode. Requires CMOS logic level signal with tr, tf < 1s. Do not "float" Pin 10. GND5 (Pin 11): 5V Section Ground. Two independent ground lines must be routed separately from other grounds to: 1) the (-) terminal of the 5V section output capacitor and 2) the cathode of the Schottky diode D2 and (-) terminal of CIN5 (see Figure 9). P-DRIVE 5 (Pin 12): High Current Drive for Top P-Channel MOSFET, 5V Section. Voltage swing at this pin is from VIN5 to ground.
UW
Off-Time vs VOUT
80 70 60 50 40 30 20 10 0 0 VOUT = 3.3V 1 3 4 2 OUTPUT VOLTAGE (V) 5
LTC1143 G11
Current Sense Threshold Voltage
175 VSENSE = VOUT 150 125 100 75 50 25 0 0 20 60 40 TEMPERATURE (C) 80 100
LTC1143 G12
MAXIMUM THRESHOLD
VOUT = 5V
MINIMUM THRESHOLD
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LTC1143/LTC1143L LTC1143L-ADJ
PIN FUNCTIONS
VIN3 (Pin 13): Supply Pin, 3.3V Section. Must be closely decoupled to 3.3V power ground Pin 3. CT3 (Pin 14): External capacitor CT3 from Pin 14 to ground sets the operating frequency for the 3.3V section. (The actual frequency is also dependent upon the input voltage.) ITH3 (Pin 15): Gain Amplifier Decoupling Point, 3.3V Section. The 3.3V section current comparator threshold increases with the Pin 15 voltage. SENSE- 3 (Pin 16): Connects to internal resistive divider which sets the output voltage for the 3.3V section. Pin 16 is also the (-) input for the current comparator on the 3.3V section. ITH2 (Pin 7): Gain Amplifier Decoupling Point, Section 2. The section 2 current comparator threshold increases with the Pin 7 voltage. SENSE- 2 (Pin 8): Pin 8 is the (-) input for the current comparator on section 2. SENSE+ 2 (Pin 9): The (+) Input to the Section 2 Current Comparator. A built-in offset between Pins 9 and 8 in conjunction with RSENSE 2 sets the current trip threshold for section 2. VFB2 (Pin 10): This pin serves as the feedback pin from an external resistive divider used to set the output voltage for section 2. GND2 (Pin 11): Section 2 Ground. Two independent ground lines must be routed separately from other grounds to: 1) the (-) terminal of section 2 output capacitor and 2) the cathode of the Schottky diode D2 and (-) terminal of CIN2 (see Figure 1). P-DRIVE 2 (Pin 12): High Current Drive for Top P-Channel MOSFET, Section 2. Voltage swing at this pin is from VIN2 to ground. VIN1 (Pin 13): Supply Pin, Section 1. Must be closely decoupled to power ground Pin 3. CT1 (Pin 14): External capacitor CT1 from Pin 14 to ground sets the operating frequency for section 1. (The actual frequency is also dependent upon the input voltage.) ITH1 (Pin 15): Gain Amplifier Decoupling Point, Section 1. The section 1 current comparator threshold increases with the Pin 15 voltage. SENSE - 1 (Pin 16): Pin 16 is the (-) input for the current comparator on section 1.
LTC1143L-ADJ
SENSE+ 1 (Pin 1): The (+) Input to the Section 1 Current Comparator. A built-in offset between Pins 1 and 16 in conjunction with RSENSE 1 sets the current trip threshold for section 1. VFB1 (Pin 2): This pin serves as the feedback pin from an external resistive divider used to set the output voltage for section 1. GND1 (Pin 3): Section 1 Ground. Two independent ground lines must be routed separately from other grounds to: 1) the (-) terminal of the section 1 output capacitor and 2) the cathode of the Schottky diode D1 and (-) terminal of CIN1 (see Figure 1). P-DRIVE 1 (Pin 4): High Current Drive for Top P-Channel MOSFET, Section 1. Voltage swing at this pin is from VIN1 to ground. VIN2 (Pin 5): Supply Pin, Section 2. Must be closely decoupled to power ground Pin 11. CT2 (Pin 6): External capacitor CT2 from Pin 6 to ground sets the operating frequency for section 2. (The actual frequency is also dependent upon the input voltage.)
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LTC1143/LTC1143L LTC1143L-ADJ FUNCTIONAL DIAGRA
Only one regulator block shown. Connections shown for LT1143/LTC1143L; changes create LTC1143L-ADJ
13(5) VIN SENSE + 4(12) 3(11) GROUND P-DRIVE 1(9) SENSE - 16(8)
SLEEP
+
S
Q S VTH1
-
VTH2
- +
T
14(6) CT
OFF-TIME CONTROL
OPERATION
Refer to Functional Diagram and Figure 1.
The LTC1143 series consists of two individual regulator blocks, each using current mode, constant off-time architectures to switch an external power MOSFET. The two LTC1143/LTC1143L regulators are internally set for 3.3V and 5V, while the two LTC1143L-ADJ regulators have externally programmable output voltages. Operating frequency is individually set on each section by external capacitors at the timing capacitor Pins 6 and 14. The output voltage is sensed by voltage comparator V and gain block G, which compare the divided output voltage with a reference voltage of 1.25V. To optimize efficiency, the LTC1143 series automatically switches between two modes of operation, burst and continuous. The voltage comparator is the primary control element when the device is in Burst Mode operation, while the gain block controls the output voltage in continuous mode. During the switch "ON" cycle in continuous mode, current comparator C monitors the voltage between Pins 1 (9) and 16 (8) connected across an external shunt in series with the inductor. When the voltage across the shunt reaches its threshold value, the P-drive output is switched to VIN, turning off the P-channel MOSFET. The timing capacitor
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-
V
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+
R
-
C 25mV TO 150mV
+
ITH 15(7)
-
+
VOS 13k G
5pF
- +
1.25V
X
VIN SENSE -
SHUTDOWN (LTC1143/LTC1143L) 2(10) VFB (LTC1143L-ADJ) X REFERENCE
100k
1143 FD
connected to Pin 14 (6) is now allowed to discharge at a rate determined by the off-time controller. The discharge current is made proportional to the feedback voltage to model the inductor current, which decays at a rate that is also proportional to the output voltage. When the voltage on the timing capacitor has discharged past VTH1, comparator T trips, setting the flip-flop. This causes the P-drive output to go low, turning the P-channel MOSFET back on. The cycle then repeats. As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage [Pin 15 (7)] to increase the current comparator threshold, thus tracking the load current. The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor continues to discharge below VTH1. When the timing capacitor discharges past VTH2, voltage comparator S trips, causing the internal sleep line to go low.
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LTC1143/LTC1143L LTC1143L-ADJ
OPERATION
The circuit now enters sleep mode with the power MOSFET turned off. In sleep mode a majority of the circuitry is turned off, dropping the quiescent current from 1.6mA to 160A (for one regulator block). The load current is now being supplied from the output capacitor. When the output voltage has dropped by the amount of hysteresis in comparator V, the P-channel MOSFET is again turned on and the process repeats. To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset (VOS) is incorpo-
APPLICATIONS INFORMATION
The basic LTC1143L-ADJ application circuit is shown in Figure 1. The LTC1143 and LTC1143L are similar but omit the external resistive VOUT dividers (see Figures 10 and 13). External component selection is driven by the load requirement and begins with VOUT and the selection of RSENSE. Once RSENSE is known, CT and L can be chosen. Next, the power MOSFET and D1 are selected. Finally, CIN and COUT are selected and the loop is compensated. Since the two regulator sections are identical, the process of component selection is the same for both sections. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 16V. Output Voltage Selection The LTC1143/LTC1143L output voltages are internally set to 3.3V and 5V. The LTC1143L-ADJ requires an external resistive divider from VOUT to VFB on each section as shown in Figure 1. The regulated LTC1143L-ADJ output voltages are given by:
R2 VOUT1 = 1.25 1 + R1 R4 VOUT2 = 1.25 1 + R3
To prevent stray pickup, a 100pF capacitor is suggested across R1 and R3 located close to the LTC1143L-ADJ.
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Refer to Functional Diagram and Figure 1
rated in the gain stage. This prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold. Using constant off-time architecture the operating frequency is a function of the input voltage. To minimize the frequency variation as dropout is approached, the off-time controller increases the CT discharge current as VIN drops below VOUT + 1.5V. In dropout the P-channel MOSFET is turned on continuously (100% duty cycle), providing extremely low dropout operation.
For Figure 1 applications with VOUT below 2V, or when RSENSE is moved to ground, the current sense comparator inputs operate near ground. When the current comparator is operated at less than 2V common mode, the off-time increases approximately 40%, requiring the use of a smaller timing capacitor CT. RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1143 series current comparators have a threshold range that extends from a minimum of 25mV/RSENSE to a maximum of 150mV/RSENSE. The current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current IMAX equal to the peak value less half the peak-to-peak ripple current. For proper Burst Mode operation, IRIPPLE(P-P) must be less than or equal to the minimum current comparator threshold. Since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., IRIPPLE(P-P) = 25mV/RSENSE. (See CT and L Selection for Operating Frequency). Solving for RSENSE and allowing a margin for variations in the LTC1143 series and external component values yields:
RSENSE = 100mV IMAX
A graph for selecting RSENSE versus maximum output current is given in Figure 2.
LTC1143/LTC1143L LTC1143L-ADJ
APPLICATIONS INFORMATION
0.20
0.15
RSENSE ()
0.10
0.05
0 0 1 3 4 2 MAXIMUM OUTPUT CURRENT (A) 5
1143 F02
Figure 2. Selecting RSENSE
CAPACITANCE (pF)
The load current below which Burst Mode operation commences, IBURST, and the peak short circuit current, ISC(PK), both track IMAX. Once RSENSE has been chosen, IBURST and ISC(PK) can be predicted from the following:
IBURST 15mV RSENSE ISC(PK) = 150mV RSENSE
The LTC1143 series automatically extends tOFF during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. The resulting ISC(AVG) to be reduced to approximately IMAX. L and CT Selection for Operating Frequency Each regulator section of the LTC1143 series uses a constant off-time architecture with tOFF determined by an external timing capacitor CT. Each time the P-channel MOSFET switch turns on the voltage on CT is reset to approximately 3.3V. During the off-time, CT is discharged by a current that is proportional to VOUT. The voltage on CT is analogous to the current in inductor L, which likewise decays at a rate proportional to VOUT. Thus the inductor value must track the timing capacitor value. The value of CT is calculated from the desired continuous mode operating frequency:
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CT =
VIN - VOUT 1.3 104 f VIN + VD 1
where VD is the drop across the diode. A graph for selecting CT versus frequency including the effects of input voltage is given in Figure 3.
1000 VSENSE = VOUT = 5V 800
600 VIN = 12V
400 VIN = 7V
200
VIN = 10V
0 0 50 150 200 100 FREQUENCY (kHz) 250
300
LTC1143 F03
Figure 3. Timing Capacitor Value
As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The complete expression for operating frequency of the circuit in Figure 1 is given by:
f 1 VOUT 1- VIN t OFF
where:
V t OFF = 1.3 104 CT REG V
OUT
V REG is the desired output voltage (i.e., 5V, 3.3V). V OUT is the measured output voltage. Thus VREG/VOUT = 1 in regulation. Note that as VIN decreases, the frequency decreases. When the input-to-output voltage differential drops below 1.5V for a particular section, the LTC1143 series reduces tOFF in that section by increasing the discharge current in CT. This prevents audible operation prior to dropout.
9
LTC1143/LTC1143L LTC1143L-ADJ
APPLICATIONS INFORMATION
Once the frequency has been set by CT, the inductor L must be chosen to provide no more than 25mV/RSENSE of peakto-peak inductor ripple current. This results in a minimum required inductor value of: LMIN = 5.1(105)(RSENSE)(CT)VREG As the inductor value is increased from the minimum value, the ESR requirements for the output capacitor are eased at the expense of efficiency. If too small an inductor is used, the inductor current will become discontinuous before the LTC1143 series enters Burst Mode operation. A consequence of this is that the LTC1143 series will delay entering Burst Mode operation and efficiency will be degraded at low currents. Inductor Core Selection Once the minimum value for L is known, the type of inductor must be selected. The highest efficiency will be obtained using Ferrite, Kool M(R) or Molypermalloy (MPP) cores. Lower cost powdered iron cores provide suitable performance, but cut efficiency by 3% to 7%. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple that can cause Burst Mode operation to be falsely triggered. Do not allow the core to saturate! Kool M (from Magnetics, Inc.) is a very good, low loss core material for toroids with a "soft" saturation characteristic. Molypermalloy is slightly more efficient at high ( > 200 kHz) switching frequencies but quite a bit more expensive. Toroids are very space efficient, especially when you can use several layers of wire, while inductors wound on bobbins are generally easier to surface mount. New designs for surface mount are available from Coiltronics, Coilcraft and Sumida. Power MOSFET Selection An external power MOSFET must be selected for use with each section of the LTC1143 series. The main selection criteria for the power MOSFETs are the threshold voltage VGS(TH), maximum VGS rating and on resistance RDS(ON). Surface mount P-channel power MOSFETs are widely available in both single and dual configurations. Logic level MOSFETs are specified for operation up to 20V maximum VGS and guarantee a maximum RDS(ON) with VGS = 4.5V. Newer `sub' logic level MOSFETs allow only 8V maximum VGS but guarantee RDS(ON) with VGS = 2.7V. If VIN will exceed 8V, logic level MOSFETs must be used; if conservatively specified, they are generally usable down to the 3.5V minimum VIN rating of the LTC1143L and LTC1143L-ADJ. The maximum output current IMAX determines the RDS(ON) requirement for the two MOSFETs. When the LTC1143 series is operating in continuous mode, the simplifying assumption can be made that either the MOSFET or Schottky diode is always conducting the average load current. The duty cycles for the MOSFET and diode are given by:
V P - Ch Duty Cycle OUT VIN Schottky Diode Duty Cycle =
10
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(VIN - VOUT + VD)
VIN
From the duty cycles the required RDS(ON) for each MOSFET can be derived:
P - Ch RDS(ON) =
() VOUT IMAX (1 + P)
VIN PP
2
where PP is the allowable power dissipation and P is the temperature dependencies of RDS(ON). PP will be determined by efficiency and/or thermal requirements (see Efficiency Considerations). (1+ P) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve,
Kool M is a registered trademark of Magnetics, Inc.
LTC1143/LTC1143L LTC1143L-ADJ
APPLICATIONS INFORMATION
but = 0.005/C can be used as an approximation for low voltage MOSFETs. When selecting the P-channel power MOSFET for each section, consideration should be given to using a dual MOSFET with the other half used for the second regulator. Assuming both sections are operating at similar currents, the required RDS(ON) will be half the value of a single MOSFET to stay within the package dissipation limit. Remember that worst-case MOSFET dissipation occurs at minimum VIN. Output Diode Selection (D1, D2) The Schottky diodes D1 and D2 shown in Figure 1 conduct during the off-time. It is important to adequately specify the diode peak current and average power dissipation to not exceed the diode ratings. The most stressful condition for the output diode is under short circuit (VOUT = 0V). Under this condition the diode must safely handle ISC(PK) at close to 100% duty cycle. Under normal load conditions the average current conducted by the diode is: RMS current must be used. The maximum RMS capacitor current is given by:
(VIN - VOUT + VD) (ILOAD) IDIODE =
VIN
Remember to keep lead lengths short and observe proper grounding (see Board Layout Checklist) to avoid ringing and increased dissipation. The forward voltage drop allowable in the diode is calculated from the maximum short-circuit current as:
VF PD ISC(PK)
where PD is the allowable power dissipation and will be determined by efficiency and/or thermal requirements (see Efficiency Considerations). CIN and COUT Selection In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle VOUT/ VIN. To prevent large voltage transients, a low effective series resistance (ESR) input capacitor sized for the maximum
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CIN Required IRMS IMAX
[(
VOUT VIN - VOUT VIN
)]
1/ 2
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. An additional 0.1F to 1F ceramic capacitor is also required on each VIN line (Pins 5, 13) for high frequency decoupling. The selection of COUT is driven by the required (ESR). The ESR of COUT must be less than twice the value of RSENSE for proper operation of the LTC1143 series: COUT Required ESR < 2RSENSE Optimum efficiency is obtained by making the ESR equal to RSENSE. As the ESR is increased up to 2RSENSE the efficiency degrades by less than 1%. If the ESR is greater than 2RSENSE, the voltage ripple on the output capacitor will prematurely trigger Burst Mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. Manufacturers such as Nichicon and United Chemicon should be considered for high performance capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR size/ratio of any aluminum electrolytic at a somewhat higher price. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. In surface mount applications multiple capacitors may have to be parallel to meet the capacitance, ESR or RMS current handling requirements of the application.
11
LTC1143/LTC1143L LTC1143L-ADJ
APPLICATIONS INFORMATION
Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. For example, if 200F/10V is called for in an application requiring 3mm height, (2) AVX 100F/10V (P/N TPSD 107M010) could be used. Consult the manufacturer for other specific recommendations. At low supply voltages a minimum capacitance at COUT is needed to prevent an abnormal low frequency operating mode (see Figure 4). When COUT is made too small the output ripple at low frequencies will be large enough to trip the voltage comparator. This causes Burst Mode operation to be activated when the LTC1143 series would normally be in continuous operation. The output remains in regulation at all times.
1000 L = 50H RSENSE = 0.02 L = 25H RSENSE = 0.02
800
COUT (F)
600
400 L = 50H RSENSE = 0.05
200
0 0 1 3 4 2 VIN - VOUT VOLTAGE (V) 5
1143 F04
Figure 4. Minimum Value of COUT
Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD x ESR, where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT until the regulator loop adapts to the current change and returns VOUT to its steady-state value.
12
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During this recovery time VOUT can be monitored for overshoot or ringing which would indicate a stability problem. The Pin 15(7) external components shown in the Figure 1 circuit will prove adequate compensation for most applications. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 * CLOAD. Thus a 10F capacitor would require a 250s rise time, limiting the charging current to about 200mA. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. (For high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power.) Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1143 series circuits: 1) 2) 3) 4) DC bias current MOSFET gate charge current I 2 R losses Voltage drop of the Schottky diode.
1) The DC supply current is the current that flows into VIN (Pin 13 and Pin 5) less the gate charge current. For VIN = 10V the DC supply current for each section is 160A for no load and increases proportionally with load up to a constant 1.6mA after the LTC1143 series has entered continuous mode. Because the DC bias current is
LTC1143/LTC1143L LTC1143L-ADJ
APPLICATIONS INFORMATION
drawn from VIN, the resulting loss increases with input voltage. For VIN = 10V the DC bias losses are generally less than 1% for load currents over 30mA. However at very low load currents the DC bias current accounts for nearly all of the loss. 2) MOSFET gate charge current results from switching the gate capacitance of the power MOSFET. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC supply current. In continuous mode, IGATECHG = (QP). The typical gate charge for a 0.05 P-channel power MOSFET is 40nC. This results in IGATECHG = 4mA in 100kHz continuous operation, for a 2% to 3% typical midcurrent loss with VIN = 10V. Note that the gate charge loss increases directly with both input voltage and operating frequency. This is the principal reason why the highest efficiency circuits operate at moderate frequencies. Furthermore, it argues against using a larger MOSFET than necessary to control I2R losses, since overkill can cost efficiency as well as money! 3) I2R losses are easily predicted from the DC resistances of the MOSFET, inductor and current shunt. In continuous mode the average output current flows through L and RSENSE, but is "chopped" between the P-channel MOSFET and Schottky diode. The MOSFET RDS(ON) multiplied by the P-channel duty cycle can be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if the RDS(ON) = 0.1, RL = 0.15, and RSENSE = 0.05, then the total resistance is 0.3. This results in losses ranging from 3% to 10% as the output current increases from 0.5A to 2A. I2R losses cause the efficiency to roll off at high output currents. 4) The Schottky diode is a major source of power loss at high currents and gets worse at high input voltages. The diode loss is calculated by multiplying the forward voltage drop times the Schottky diode duty cycle multiplied by the load current. For example, assuming a duty cycle of 50% with a Schottky diode forward voltage drop of 0.4V, the loss increases from 0.5% to 8% as the load current increases from 0.5A to 2A. If Schotky diode losses routinely exceed 5% consider using the synchronously switched LTC1142 series. Figure 5 shows how the efficiency losses in one section of a typical LTC1143 series regulator end up being apportioned. The gate charge loss is responsible for the majority of the efficiency lost in the midcurrent region. If Burst Mode operation was not employed at low currents, the gate charge loss alone would cause efficiency to drop to unacceptable levels. With Burst Mode operation, the DC supply current represents the lone (and unavoidable) loss component, which continues to become a higher percentage as output current is reduced. As expected, the I2R losses and Schottky diode loss dominate at high load currents. Other losses including CIN and COUT ESR dissipative losses, MOSFET switching losses and inductor core losses, generally account for less than 2% total additional loss.
100 GATE CHARGE 95
EFFICIENCY (%)
1 LTC1143 I 2 Q
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W
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I2R
90
SCHOTTKY DIODE
85
80 0.01
0.03
0.3 1 0.1 OUTPUT CURRENT (A)
3
LTC1143 * F05
Figure 5. Efficiency Loss
Shutdown Considerations Pins 2 and 10 on the LTC1143 and LTC1143L shut down their respective sections when pulled high. They require CMOS logic level signals with tr, tf < 1s and must never be floated. The LTC1143L-ADJ gives up the pin-controlled shutdown function in order to gain feedback pins for programming the output voltages.
13
LTC1143/LTC1143L LTC1143L-ADJ
APPLICATIONS INFORMATION
The LTC1143L-ADJ outputs can be turned off in one of two ways: 1) by placing a power MOSFET switch in the VIN line to the entire regulator or 2) by pulling the VFB pin over 1.4V, which trips comparator V and forces P-DRIVE high (see Functional Diagram). VFB can be pulled high with a small current, but any circuitry used to shut down the LTC1143L-ADJ in this manner must minimize VFB lead length to prevent noise coupling during normal operation. In the Figure 6 circuit, taking SHUTDOWN high turns on PNP QSD that sources a current into VFB. To shut down properly, RSD must be chosen to pull VFB above 1.4V with VOUT at 0V and minimum VIN. Note that this technique depends on the load resistance to prevent VOUT from floating up due to the current flowing into VFB.
VOUT R2 QSD VFB 100pF R1 50k 100k SHUTDOWN
1143 F06
VIN RSD 200k
Figure 6. Local VFB Pull-Up Shuts Down LTC1143L-ADJ
Design Example As a design example, assume VIN = 12V(nominal), VOUT = 3.3V, IMAX = 2A and = 200kHz. RSENSE, CT and L can immediately be calculated: RSENSE = 100mV/2 = 0.05 tOFF = (1/200kHz)[1 - (3.3/12)] = 3.63s CT = 3.63s/(1.3 x 104) = 280pF (use 300pF) LMIN = 5.1(105 )(0.05)(300pF) 3.3V = 25H Assume a dual P-channel power MOSFET is to be used and dissipation is to be limited to 1W total at worst-case lowest VIN = 4V. If TA = 50C and the thermal resistance of the MOSFET package is 50C/W, then the junction temperature will be 100C and
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U
P = 0.005(100 - 25) = 0.38. The maximum RDS(ON) for each MOSFET can now be calculated: 41 1 P - Ch RDS(ON) = 2 2 3.3 2 1.38
( ) = 0.11 ( ) ( )
Allowing for V IN being slightly below the VGS used to specify RDS(ON), this requirement can be met by half of a Siliconix Si4953DY, Fairchild NDS8947 or similar SO-8 dual P-channel MOSFET. The most stringent requirement for the Schottky diode is with VOUT = 0V (i.e. short circuit). During a continuous short circuit, the worst-case Schottky diode dissipation rises to:
V PD = ISC(AVG) VD 1 - OUT VIN
()
With the 0.05 sense resistor, ISC(AVG) = 2A will result, increasing the 0.4V Schottky diode dissipation to 0.8W. CIN will require an RMS current rating of at least 1A at temperature and COUT will require an ESR of 0.05 for optimum efficiency. Troubleshooting Hints Since efficiency is critical to LTC1143 series applications it is very important to verify that the circuit is functioning correctly in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the timing capacitor Pins 6 and 14. In continuous mode (ILOAD > IBURST) the voltage on the CT pin should be a sawtooth with a 0.9VP-P swing. This voltage should never dip below 2V as shown in Figure 7a. When load currents are low (ILOAD < IBURST) Burst Mode operation occurs. The voltage on the CT pin now falls to ground for periods of time as shown in Figure 7b. If Pin 6 or Pin 14 is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist.
LTC1143/LTC1143L LTC1143L-ADJ
APPLICATIONS INFORMATION
3.3V
(a) CONTINUOUS MODE OPERATION 3.3V
(b) Burst Mode OPERATION
Figure 7. CT Waveforms
Auxiliary Windings--Suppressing Burst Mode Operation The LTC1143 series operates nonsynchronously with the normal limitation that the power drawn from the inductor primary winding must not be less than twice the power drawn from the auxiliary windings. (With synchronous switching, using the LTC1142 series, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation.) Burst Mode operation can be suppressed at low output currents with a simple external network that cancels the 25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from certain types of inductors in high current (IOUT > 5A) applications when they are lightly loaded. An external offset is put in series with the Sense- pin to subtract from the built-in 25mV offset. An example of this technique is shown in Figure 8. Two 100 resistors are inserted in series with the sense leads from the sense resistor.
SENSE + [PIN 16 (8)] 1000pF SENSE - [PIN 1(9)] R3 R2 100 R1 100 RSENSE VOUT
+
COUT
1143 F08
Figure 8. Suppression of Burst Mode Operation
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With the addition of R3 a current is generated though R1, causing an offset of:
R1 VOFFSET = VOUT R1 + R3
0V
0V
LTC1143 * F07
If VOFFSET > 25mV, the built-in offset will be cancelled and Burst Mode operation is prevented from occurring. Since VOFFSET is constant, the maximum load current is also decreased by the same offset. Thus, to get back to the same IMAX, the value of the sense resistor must be lower:
RSENSE
75mV IMAX
To prevent noise spikes from erroneously tripping the current comparator, a 1000pF capacitor is needed across Pins 1 (16) and 9 (8). Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1143 series. These items are also illustrated graphically in the layout diagram of Figure 9. In general, each block should be self-contained with little cross coupling for best performance. Check the following in your layout: 1) Are the signal and power grounds segregated? The LTC1143 series GND Pin 3 (11) must return separately to: a) the power and b) the signal grounds. The power ground returns to the anode of the Schottky diode and (-) plate of CIN, which should have as short lead lengths as possible.The signal ground (b) connects to the (-) plate of COUT. 2) Does the LTC1143 series SENSE - Pin 16 (8) connect to a point close to RSENSE and the (+) plate of COUT? 3) Are the SENSE- and SENSE + leads routed together with minimum PC trace spacing? The 1000pF capacitor between Pins 1 (9) and 16 (8) should be as close as possible to the LTC1143 series. 4) Does the (+) plate of CIN connect to the source of the P-channel MOSFET as closely as possible? This capacitor provides the AC current to the P-channel MOSFET.
15
LTC1143/LTC1143L LTC1143L-ADJ
APPLICATIONS INFORMATION
5) Is the VIN decoupling capacitor (1F, 0.1F) connected closely between Pin 13 (5) and GND Pin 3 (11)? This capacitor carries the MOSFET driver peak currents. 6) For the LTC1143 and LTC1143L, are the SHUTDOWN Pins 2 and 10 actively pulled to ground during normal operation? Both SHUTDOWN pins are high impedance and must not be allowed to float. Both pins can be driven by the same external signal if needed. 7) For the LTC1143L-ADJ, are the VFB Pins 2 and 10 decoupled with 100pF as close to the device as possible? The VFB line is sensitive to noise pickup and should be kept away from the P-channel MOSFET.
+
VIN5
+
CIN5
-
SHUTDOWN (5V OUTPUT)
1k
P-DRIVES5
GND5
SHUTDOWN 5
SENSE -3
CT3
0.0033F
SENSE +5
ITH3
CT3 VIN3
LTC1143
SHUTDOWN 3
1000pF*
SENSE +3
-5
0.22F*
P-DRIVES3 VIN5
GND3
SHUTDOWN (3.3V OUTPUT)
VIN5 1k CT5 0.0033F
+ +
VOUT3
RSENSE3
L2
P-CH
CT5
SENSE
ITH5
COUT3
-
*MUST BE LOCATED CLOSE TO LTC1143 BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 9. LTC1143 Layout Diagram (see Board Layout Checklist)
16
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P-CH
L1
RSENSE5
+ +
COUT5 VOUT5
D1
-
VIN3
1000pF* 0.22F*
+ +
CIN3 VIN3
D2
-
1143 F09
LTC1143/LTC1143L LTC1143L-ADJ
TYPICAL APPLICATIONS
VIN RANGE VOUT5 ON: 5.2V TO 8V VOUT5 SHUTDOWN: 3.5V TO 8V CIN3 22F 25V x2
+
13 VIN3
P1A VOUT3 3.3V/1A RSENSE3 0.10 L1 50H 4 1 0.01F
+
COUT3 220F 10V
D1 MBRS140T3
CIN3, CIN5: AVX TPSD226K025R0200 COUT3, COUT5: AVX TPSE227M010R0080 L2: COILTRONICS CTX50-4 L2: COILTRONICS CTX25-4 P1: FAIRCHILD NDS8934 RSENSE3: IRC LR2512-01-OR100G RSENSE5: IRC LR2512-01-ORO5OG
Figure 10. All Surface Mount Low Dropout Dual 5V/2A, 3.3V/1A Converter
+
CIN1 22F 25V x3 L1 15H
0.22F P1 4 1 13 VIN1 P-DRIVE 1 SENSE + 1 LTC1143L-ADJ 16 SENSE - 1 SENSE - 2 8 5 VIN2 P-DRIVE 2 SENSE + 2
VOUT1 1.8V/3A
RSENSE1 0.025
100 COUT1 330F 6.3V x2
100
1000pF
+
R2 22.1k 1% R1 49.9k 1%
D1 MBRS320T3
5.6k
100pF
CIN1, CIN2: AVX TPSD226K025R0200 COUT1: AVX TPSE337M006R0100 COUT2: AVX TPSE227M010R0100
Figure 11. Dual 1.8V/3A and 2.5V/2A with Burst Mode Defeated
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16
+
0.22F 0V = NORMAL >1.5V = SHUTDOWN 2 SHUTDOWN 3 10 SHUTDOWN 5 0.22F
+
5 VIN5 P-DRIVE 5 SENSE + 5 SENSE - 5 12 9 0.01F 8
+
CIN5 22F 25V x2
P1B L2 25H RSENSE5 0.05 VOUT5 5V/2A
P-DRIVE 3 SENSE + 3 SENSE - 3 GND3 3 CT3 14 ITH3 15 RC3 1k CT3 270pF CC3 3300pF ITH5 7 RC5 1k CC5 3300pF CT5 6
LTC1143L
+
D2 MBRS140T3
GND5 11
COUT5 220F 10V x2
1143 F10
CT5 220pF
VIN 4V TO 14V
+
0.22F P2 12 9 1000pF 8.2k VFB1 GND1 3 CT1 14 ITH1 15 RC1 510 CC1 CC2 3300pF 3300pF ITH2 7 RC2 1k CT2 300pF CT2 6 VFB2 GND2 11 10 100pF 100pF 100 100 L2 27H
CIN2 22F 25V x2 RSENSE2 0.04
VOUT2 2.5V/2A
D2 MBRS320T3
R4 49.9k 1% R3 49.9k 1%
+
2
COUT2 220F 10V x2
CT1 220pF
L1: SUMIDA CDRH125-150 L2: SUMIDA CDRH125-270
P1: IR IRF7406 P2: IR IRF7204
RSENSE1: DALE WSL-2010-.025 RSENSE2: DALE WSL-2010-.04
1143 F11
17
LTC1143/LTC1143L LTC1143L-ADJ
TYPICAL APPLICATIONS
+
CIN1 22F 25V x2 L1 27H
0.22F P1 4 1 1000pF 13 VIN1 P-DRIVE 1 SENSE + 1 LTC1143L-ADJ 16 SENSE - 1 SENSE - 2 8 5 VIN2 P-DRIVE 2 SENSE + 2 12
VOUT1 3.3V/2A
RSENSE1 0.05
COUT1 220F 10V x2
+
R2 82.5k 1% R1 49.9k 1%
D1 MBRS130L
2 100pF
CIN1, CIN2: AVX TPSD226K025R0200 COUT1, COUT2: AVX TPSE227M010R0100 L1: SUMIDA CDRH125-270 L2: PULSE ENGINEERING PE-53718
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VIN 3.5V TO 10V P2 0.22F 220F 10V
+ +
L2B
CIN2 22F 25V x2 VOUT2 5V/1A
L2A 9 1000pF RSENSE2 0.082
D2 MBRS130L
VFB1 GND1 3 CT1 300pF CT1 14 ITH1 15 RC1 1k CC1 3300pF ITH2 7 RC2 1k CC2 3300pF CT2 6 CT2 180pF
VFB2 GND2 11
R4 150k 1% R3 49.9k 1%
COUT2 220F 10V
10 100pF
OVERVOLTAGE PROTECTION
Z1 5.1V 1k
1143 F12
P1, P2: SILICONIX Si9803DY RSENSE1: IRC 1206-R050F RSENSE2: IRC 1206-R082F Z1: MMBZ5231B
MMBT2222ALT1
Figure 12. Dual 3.3V/5V Buck-Boost Regulator
LTC1143/LTC1143L LTC1143L-ADJ
PACKAGE DESCRIPTION
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0 - 8 TYP
0.016 - 0.050 0.406 - 1.270 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Dimensions in inches (millimeters) unless otherwise noted.
S Package 16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 - 0.394* (9.804 - 10.008) 16 15 14 13 12 11 10 9
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.346 - 1.752)
2
3
4
5
6
7
8
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
S16 0695
19
LTC1143/LTC1143L LTC1143L-ADJ
TYPICAL APPLICATION
VIN 5.2V TO 14V CIN3 22F 25V x3
+
13 VIN3 4 1 0.01F 16
P1 VOUT3 3.3V/3A RSENSE3 0.033 L1 10H
+C
OUT3
220F 10V x3
D1 MBRD340
CIN3, CIN5: AVX TPSD226K025R0200 COUT3, COUT5: AVX TPSE227M010R0080 L1: COILTRONICS CTX10-4 L2: COILTRONICS CTX25-4
Figure 13. All Surface Mount Dual 5V/2A, 3.3V/3A Converter
RELATED PARTS
PART NUMBER LTC1142 LTC1142L-ADJ LTC1147L LTC1265 LTC1438 LTC1538-AUX LTC1539 DESCRIPTION Dual High Efficiency Synchronous Step-Down Switching Regulator Dual High Efficiency Synchronous Step-Down Switching Regulator High Efficiency Step-Down Switching Regulator Controller 1.2A, High Efficiency Step-Down DC/DC Converter Dual Synchronous Controller with Power-On Reset and an Extra Comparator Dual Synchronous Controller with Auxiliary Linear Regulator Controller and 5V Standby Dual Synchronous Controller with Phase-Locked Loop and Adaptive PowerTM Operation COMMENTS Synchronous Equivalent to LTC1143, 4V < VIN < 16V Synchronous Equivalent to LTC1143L-ADJ, 3.5V < VIN < 16V 4V < VIN < 20V (1/2) LTC1143L-ADJ in SO-8 Single Channel with Internal Switch Constant Frequency Current Mode, Drives Synchronous N-Channel MOSFETS Up to Four Output Voltages from G28 Package Full Featured Dual Controller in G36 Package
LTC1142HV-ADJ Dual High Efficiency Synchronous Step-Down Switching Regulator
Adaptive Power is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
U
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0.22F 2 SHUTDOWN 3 0V = NORMAL >1.5V = SHUTDOWN 0.22F 10 SHUTDOWN 5
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5 VIN5 P-DRIVE 5 SENSE + 5 12 9 0.01F
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CIN5 22F 25V x2
P2 L2 25H RSENSE5 0.05 VOUT5 5V/2A
P-DRIVE 3 SENSE + 3
LTC1143
SENSE - 3 GND3 3 CT3 14 ITH3 15 RC3 510 CC3 3300pF ITH5 7 RC5 1k CC5 3300pF CT5 6
SENSE - 5 GND5 11
8 D2 MBRD340
+
COUT5 220F 10V x2
CT3 200pF
CT5 220pF
LTC1143.F13
P1: SILICONIX Si4431DY P2: SILICONIX Si9435DY RSENSE3: KRL SL-1/2-C1-0R033J RSENSE5: KRL SL-1/2-C1-0R050J
1143fa LT/TP 0598 REV A 2K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1994

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